The whole chip, as one schematic.

This is the tracer's containers made disjoint: the same derivations, applied in the tracer's own click order, the first container to reach a node keeping it. What no container claims is grouped by the block it is filed in, and the static logic by the block its gates drive. Nothing here is a floorplan and nothing is a guess: both axes of the layout are measurements, and the caption counts what the bundles carry.

The tour walks ADC across the map, one authored sentence per step. The narration was written from a per-half-cycle dump of that exact program on the engine, and it is the weaker register: prose goes quietly wrong, because nothing re-reads it. So every claim it makes rides beside a check the page evaluates on the running chip at that step, the moved list under it is the change set grouped by the partition, and the harness re-evaluates every check on a chip of its own. If the narration and the silicon ever disagree, the tick goes red on the page rather than in a footnote.

The steps are offsets from the instruction's own opcode fetch, found by running until sync with its address on the bus; the address comes from the assembler's label. The header transport keeps working during the tour, and stepping off the authored path says so and offers the way back, because the panel reads the machine rather than counting its own clicks.

A column is how far a group sits from the outside world: the median, over its nodes, of each node's distance from the input and bidirectional pins, walking gate inputs to the outputs they help produce and both ways through a switch channel. The pins land in the first column, the deepest control logic about sixteen hops in, and the two inert structures the pins can never reach are the last column, which is the honest place to put them.

The order within a column is the median die position of the group's members, from the same polygons the die view draws. That is what keeps the address machinery beside the address machinery: the picture agrees with the exploded view about what is near what, without borrowing anything from it.

The boxes open. Each container's members sit snapped to a grid inside it, in a stated order: a name carrying a bit index sorts by stem then bit, so a byte reads left to right from bit 0; other names follow alphabetically; the unnamed come last in die order. The boxes also drag: your own arrangement, snapped to the same grid, kept across visits, and given back by Tidy in one press; the derived layout stays the page's claim, and a moved box is yours. Save writes the arrangement as one small file, a container key to its x and y offset and nothing else; Load applies one, skipping and counting anything it does not recognise. Scramble throws every box somewhere else, seeded so the first throw is always the same throw, and Optimize untangles by physics: every pair of boxes repels, every bundle pulls its ends together with a strength scaled by the edges it carries, and the step size cools until it settles. It runs unwalled: pairwise forces are equal and opposite, so the cloud stays put on its own and takes whatever size the balance wants, with the camera following it and Fit framing wherever the boxes actually are. One weak force remains: a gravity toward the cloud's own centroid, proportional to distance, because a container with no bundles at all feels pure repulsion and would otherwise accelerate away for as long as the cooling lets it. Measured before the gravity existed: one reached thirty-one thousand units out. And boxes never settle overlapping: intersecting pairs are pushed apart along the smaller penetration axis, over and over until none remain, with a clearance the snap cannot steal back, so a settled arrangement can touch but never stack. The note reports the stretch, the sum over bundles of weight times centre distance, before and after; that number is the measurement, and whether the result reads better than the derived columns is yours to judge. Tidy remains the way back. A square is a node that holds switches, filled while its switches conduct and empty while they are open circuit; everything else is a dot, lit while it is high and ringed when it changed at the last half-cycle. Clicking a glyph names the node on the card. The Nodes button folds the grids away, and ?nodes=0 arrives folded.

A line is a bundle: every gate edge and every pass transistor joining two groups, drawn once and weighted by the count. The brighter bundles are the ones carrying switches, the same distinction every drawing on this site keeps, because a switch joins two wires without either causing the other. Nothing is thresholded away; a one-edge bundle is simply faint.

Every colour on this page is one of two claims, and they are the same two claims every drawing on this site makes. The key below is drawn with the drawing's own classes, so it cannot drift from what it documents.

Run the chip at the slowest clock and the moving lights read in order: the decode-term boxes light stage by stage, because a term named for a T-state fires in that state, which is the measurement the decode and timing pages record. The clock generator is the one box that is always ringed, because all of its nodes move at every half-cycle, which is what a clock generator is.

Membership is solved outright: every box is a measured closure or cone from the switch network, and every node is in exactly one. The circuitry inside is solved at the gate level: the static gates are recognised from the NMOS structure itself, and the workbench will draw any of them. The meaning is solved where the die's names and the derivations reach: what each register line loads, which wire SYNC really is, why the NMI path touches exactly the address bit that tells its vector apart.

Two honest gaps remain, and the boxes carry them rather than hiding them: the pipeUNK latches, named by the original reverse engineers for precisely what they could not yet name, and the unnamed static gates, which are identified as gates and attributed to the block they drive but not individually storied. That is the map's remaining dark matter, and it is drawn in the same grid as everything else.

The header transport drives the same simulation as every other page. A box fills with the share of its members high right now and rings when any of them changed at the last half-cycle; a switch bundle brightens while one of its control lines holds it open, and a gate bundle flashes when one of its outputs moved. Watch one instruction at the slowest clock and the fetch runs left to right: pins, data latch, instruction register, decode terms, control lines, datapath.

Clicking a box is the walk. The card lists the heaviest bundles as pills that select the far end, and links to the same container on the tracer, where the identical set of nodes sits at its die positions instead of in a diagram.

The tracer's containers overlap on purpose: the decimal correction runs through the ALU's slices, and a click resolves the overlap by priority. A schematic needs the opposite, so this page applies the same priority as ownership. That order decides real things: the pipeline latch file outranks the timing chain, so the chain's own re-timing latches file with the latch file and the chain keeps its combinational cells; the address latches outrank the store pipeline, so the hold logic their load line reads files with the latches. The boxes say what survived, and the tracer link on each card shows the container whole.

The containers are derived from the switch network of the die trace by Greg James, Brian Silverman, Barry Silverman and Ed Spittles, licensed CC BY-NC-SA 3.0. Those terms carry to everything on this site.

The tracer The die graph Credit and licence