One gate shape,
1160 times.

Every gate on this page was found by looking at what a node is wired to. A pullup with one transistor to ground is an inverter. With several in parallel, a NOR. With several in series, a NAND. With both, and-or-invert, which NMOS builds as easily as the simple cases and which is why the decode PLA is so compact.

That rule resolves every pullup node on the die but one, and the one it does not is reported rather than smoothed over: a series chain three deep, past what this recognises.

Keyed on pullups alone, the most interesting signals on the chip come back empty. dpc3_SBX, dpc23_SBAC and sync have no pullup, and the first version of this page showed them as dead ends: a control line with nothing behind it.

They are precharged. A clocked transistor pulls the node up, and the pulldown network either discharges it or leaves it holding its charge for the rest of the cycle. Same sum-of-products shape, different way of being held high, and 150 nodes work this way, including every control line the datapath obeys. It is the same dynamic storage the simulator models as a charged node, and the reason this chip has a minimum clock speed as well as a maximum: stop it too long and the charge, which is the state, leaks away.

A datapath is supposed to be eight copies of one circuit. This one looks like it: the Blueprint shows bit index running cleanly down the die with each unit holding its column. The obvious next step is to draw one bit and write “×8”.

It does not survive contact with the wiring. Running structural refinement over the whole netlist, on pure graph shape with no names, puts every bit of every bus in its own class. Not one bus collapses. Compare any two bits above and the differences have names: bit 7 of the special bus is opened by ADDSB7 while bits 0–6 share ADDSB06, because bit 7 is where the shifter is. adh carries constant generators on two bits and not the others. The carry chain links each bit to its neighbour, so no bit sees the same thing as any other.

The datapath is geometrically regular and electrically irregular. The regularity is in the layout, which is what made it buildable by hand; the irregularity is the design. Collapsing the picture to one slice would have hidden exactly the parts that make the chip work.

1160 symbols absorb 2637 of 3510 transistors; the remaining 873 stay as switches, because that is what they are: the die uses them to steer signals, not to compute with them. The two numbers add to exactly 3510, which is checked rather than assumed.

One rule earns its place there. Two switches in a row really do pull an output down, so a chain of them reads as a single gate with a two-input series leg, and that reading is electrically true wherever it fires. But it is only the right reading when the node in the middle is a junction. The ALU's A input sits between the special bus and ground, fed through SBADD and forced low through 0ADD, and reading it as a series leg swallowed both of its transistors, leaving alua0…alua7 with no visible circuit at all, on a page whose entire job is to show what makes a signal. A gate's internal junction drives nothing; a node that gates transistors of its own is a signal. That one distinction fixed it, and took the last of the double-counted pulldowns with it.

A switch's control line is drawn as a label rather than followed. Expanding it would be honest and useless: cclk alone gates 273 transistors, so following controls pulls the entire clock tree into view within two levels and buries the signal you asked about. Click a control line to make it the subject instead.

The same walk runs either way. Backwards it asks what produces a value: the gate that drives it, and the wires a switch could bring to it. Forwards it asks what the value changes: the gates it is an input to, and the switches it opens, which for a control line is the entire reason it exists.

Pass transistors appear in both, and that is not a hedge. A pass transistor genuinely conducts both ways; the parts that have a direction are the gate and the control line, and those are the parts that differ between the two readings.

Fan-out is capped at 16 and the cap is declared. Most signals drive one or two things (the median is one) but cclk opens 273 switches and the instruction register's bits feed dozens of product terms. A picture that quietly showed sixteen of those would be a claim about the chip rather than a limit of the page, so the caption says how many it left out.