Nothing here is laid out
The graph, drawn where the silicon put it.
Every other drawing on this site chooses an arrangement. The schematic lays a cone out in columns, the blueprint stacks buses as rails, the block diagram places boxes by rule. This one decides nothing: each node sits at its own centroid on the die and each line is a connection the netlist already has.
Loading the chip…
A chip is a graph that was already embedded in a plane, by the people who drew it, forty years before anyone thought to ask a computer for a layout. That embedding is not lost and does not have to be inferred: it is in the polygons, and this page reads it out and connects it up.
How to read it
Two relations, and a colour that is a measurement
A brighter line is a pass transistor joining two wires: neither end causes the other, and that is what a datapath is made of. A dimmer line is a gate input reaching the output it helps produce, which is what logic is made of. Keeping them apart is the same distinction the block pages draw on their boundary panels, and it is why the datapath shows up as structure rather than as more of the same.
The colour of a node is which functional block blocks.rs filed it under, grown out of the die's own names. It is the same palette the exploded view uses, so a region that looks like one thing here looks like the same thing there. That colouring is a measurement rather than a decoration, which is the reason the clusters mean anything at all.
The rails are not drawn. Ground and supply touch most of the chip, so including them would put a star through the middle of the picture and say nothing that the count of their connections does not say better.
Why the default is the smaller one
The density is itself the finding
Named signals come to a drawing a person can read. Every node roughly doubles it, and the second half is almost entirely gate outputs nobody needed to name: the inverters and NORs that the functional blocks are embedded in. Switching the view over is worth doing once, because the thing it shows is not a prettier picture but a true proportion. Most of this chip is logic, and the logic does not thin out anywhere.
That matches what the other pages measure from their own directions. The blueprint can honestly draw only the bus fabric, a small slice of a chip that is mostly pulldowns. The block pages find that a functional block is not a closed circuit, because its gates are built out of static logic no block claimed. This is the same fact seen from above.
The positions come from the same geometry the die view draws, so a cluster here is in the place you can go and look at there.
Credit
Sources
The positions and the connections are both from the die trace by Greg James, Brian Silverman, Barry Silverman and Ed Spittles, licensed CC BY-NC-SA 3.0. Those terms carry to everything on this site.