A transistor is
a crossing.

The die data distinguishes six kinds of polygon, but three of them (switched, grounded and powered diffusion) are the same physical layer, coloured by what it happens to be tied to. Green is ground, red is power, amber is everything doing work. So the layer slider lifts three heights apart, not six.

Poly crossing metal does nothing; they are insulated and simply pass over each other. Diffusion crossing metal does nothing either, unless somebody placed a contact. Poly crossing diffusion is the exception, and the exception is the entire computer: put a voltage on the poly and its field reaches through the oxide to pull the silicon beneath it into conducting, joining the diffusion on either side. Take it away and the channel closes.

That is why the filaments are drawn where they are. Each one stands at a transistor's own bounding box, running from the diffusion it switches to the poly that gates it, and brightens when that gate goes high. Run the chip with the layers lifted and you are watching the switches switch.

The second slider slides the functional blocks apart. Each keeps its real polygons and its real place. They move outward from the middle of the die in the direction they already lie, then nudge each other until they stop overlapping, so the arrangement stays recognisable as the chip.

Which node belongs to which block is derived, not drawn. It rests on the same fact the decode table does: the die names itself. The adder's carry chain is named bit by bit, its intermediate products are named as the logic they compute, the program counter's precharge nodes are named, and every product term of the decode PLA is named after the instructions it serves. Those names are the seeds; anything unnamed is grown in from what it is wired to.

Growth follows the wiring, never the gates. A node gated by a decode line is being told what to do by the decoder, which is the opposite of belonging to it. Follow gates and the PLA swallows the chip in three rounds.

Nodes the die named outright are drawn brighter than nodes inferred from their neighbours, because those are different strengths of claim and the picture should say which one it is making.

Twelve functional blocks account for 2448 transistors. The other 1060 are not a ragged edge that resisted classification. They are one thing, and the chip is built out of them: the static gates. Inverters and NORs, the part of the 6502 that is not pass transistors.

They stayed outside the blocks for a structural reason rather than by accident. A static gate's output touches nothing but its pullup to +5V and its pulldown to ground, and the growth rule refuses to cross a power rail, a rail touches hundreds of transistors, and crossing one would merge the whole chip into a single block. So no path exists from a named wire to a gate output, however close together they sit. The bus fabric is connected and reachable; the logic is 511 islands surrounded by power, the largest holding three nodes and 447 of them a single node.

Which is what a logic gate looks like. They are identified here by the electrical signature that defines one (a pullup, or a terminal on ground) and 856 of their 1060 transistors are pulldowns, which is the other half of the same fact.

They do not move when the blocks explode. A gate can be attributed to the block it feeds, and 351 of them are, but attribution is not location: a quarter of those sit more than 3000 die units from what they drive, because control signals are generated beside the decoder and consumed in the datapath. Moving a gate to the block it drives would be inventing a floorplan. So the logic stays exactly where it is, and what you see at full explode is the functional blocks lifting away from the web of gates they were embedded in.

After all that, two transistors and four nodes are left, and they are the most interesting thing here, because they do nothing at all.

They form two isolated structures near the top edge of the die. The first is a transistor whose gate connects to nothing else on the chip: no wire can drive it, so it can never switch, and its channel ties a dead-end node to +5V. The second is a real transistor, gated by the pipeline clock, that genuinely opens and closes every cycle, joining two nodes that connect to nothing and gate nothing.

A node influences this chip in exactly one way: by gating a transistor. Every node in both structures either gates nothing, or has no connection through which anything could drive it. So they are not unclassified so much as inert: present in the photograph, absent from the computer. They are still drawn, still fading in the middle at full explode, because a thing that cannot be explained is worth more on the page than off it.

It is worth being plain about what this is not: nobody has MOS's original floorplan, and this is an inference from a photograph of a chip. A boundary here is where the names and the wiring say one part stops, not where a draughtsman drew a line in 1975.