The whole circuit, one half-cycle at a time.

The drawing is the die graph with a clock. Nothing in it is laid out: each node sits at its own centroid on the die, so the address latches are where the address latches are, and the bits of a bus run down the chip the way they run down the silicon. What the simulation adds is the level of every node, and the difference between one half-cycle and the next.

A filled node is high and a dark one is low, in the colour of the functional block that owns it. A bright ring is a node whose level changed at this half-cycle; a fainter ring is one that changed at the previous one, so a wave of activity reads as motion rather than as a flicker. A brighter line is a pass transistor whose control is high, so the two wires it joins are one wire for the moment; a line that flashes is a gate whose output just moved. Every one of those marks is a comparison of two readings of the chip, taken by this page.

The tinted regions behind the graph are the functional blocks, each in the colour its nodes wear, and each is a rule rather than a drawing: everything on the die within a fixed distance of one of the block's nodes. A block can come out in several pieces, and two blocks' regions can overlap; both happen, and the caption under the drawing counts them. Click a region to select its block: the region brightens, the rest of the drawing steps back, the block card says how many of its nodes are drawn and how many moved at this half-cycle, and the moved list marks its group. Where regions overlap, the click goes to the block with the nearest node, which is the same rule that drew them. The thinner capsules inside them are the buses and latches: every stem the die names bit by bit, a byte (or the sixteen address pins) drawn as everything within a shorter distance of one of its bits, with its name above it. Click a capsule to select the bus: the card reads its value now and how many bits moved, and offers to watch it. A capsule wins over the region it sits in, being the more specific claim. The dashed outlines are the static logic in clusters. Those gates belong to no block and have no natural spacing of their own, so the grouping is two-level and stated: by the block a gate drives, which is the attribution the block pages use, then by proximity. A gate on its own is not a cluster and is left out, counted in the caption. A cluster is tinted by the block it drives, lavender when it drives no single block; click one and the card says how many gates, which block, how many are high and how many moved. A capsule wins over a cluster, and a cluster over the block region under it. The beads along the decode PLA are its product terms, clustered by the stage their names serve: the die calls a term op-T0-lda or op-T2-ind-y, and a name with no T-state serves any stage. That cluster is a set rather than a place, because the stages are interleaved along the row of terms, so its beads are scattered and coloured by stage, warm early to cool late. Click one to select the stage: the card says how many of its terms are high at this half-cycle and names them, which is the decoder's answer to what the chip is doing right now. The dotted outlines in the datapath are the decode control lines, clustered by what they operate: each line gates a row of transistors, and the block most of those are filed in is the unit it drives. The lines for the registers, the ALU, the address latches, the data bus and the program counter each sit together beside their unit, and a few gate static logic rather than switches and are filed with it. Click one to select the set: the card names the lines that are high at this half-cycle and counts the switches they are holding open. A control cluster wins over a capsule, being smaller. The halos on the pads are the pins, grouped by the direction the pinout page measures from the switch network: a pin is an output if a gate that can pull down drives it, an input if it feeds gates, and both if both, which is how the data pins come out bidirectional with nobody saying so. The group is a set around the ring, so its halos are scattered; click one and the card reads every pin of that direction, its level, and which moved. The address and data pads are also capsules, and a halo reaches past the capsule on purpose so it can still be clicked at the pad's edge. The long-dashed beads are the timing chain as cells, one per T-state the simulator's readout reads, and they were derived rather than taken from the timing-chain block, which is a set of names spread into a dozen pieces with the chain's own latches filed elsewhere. From each of the six outputs the rule walks back through gate inputs and switch channels, inside the timing chain, the control pipeline and the static logic, stopping where a node reads anything from outside; each node goes to the stage that reaches it soonest, a tie is shared, and so is anything three or more stages read, which is the reset and the ready. What comes out for T2 to T5 is the same five nodes each: the output, the NOR behind it, the cclk half-latch the die calls pipeT3out, a dynamic node loaded through cp1, and the AOI that reads ready and the previous stage's latch, or not-ready and its own: a shift register that holds when RDY is low, written out in switches. T0 is larger because it is the state the chain is reset into, so its cell is the end-of-instruction logic up to the boundary. A cell wears the hue of its stage, so the decode terms for T3 and the chain's T3 match; click one and the card says whether the state is active now by the chip's own readout (the outputs are active low), names the nodes, and says which other cell it reads, which is the chain's order read off the wires. The bright outline is the clock generator, the circuit the designer page derives and the tracer takes from the same module: walk forward from the clk0 pad through gate inputs, include the four clocks it ends at, never expand them. Sixteen nodes and forty-four transistors, of which twenty-one decide anything and the rest are the four output stages; two transistors gated by a generated clock land back inside it, and that feedback is the non-overlap the whole circuit is on the die for. Click it and the card reads the four clocks' levels off the chip and names what moved at this half-cycle, which at any clock is the generator itself. The double-ringed beads are the interrupt logic, and the pins give it its structure: from each of irq, nmi and res the rule walks forward through gate inputs and switch channels, inside the interrupts block and the static logic it is built from, stopping where a node feeds anything outside, which is where an interrupt stops being detected and starts being acted on. What one pin alone reaches is that pin's path; what two reach is shared, and that is four nodes ending at INTG, the interrupt-go. The vector selection is not reached from any pin, because the BRK sequence drives it, so it is grouped by the die's own names; and the NMI path reaches pipeVectorA2 on its own, which is the one address bit by which the NMI vector differs from the IRQ vector. The block the names seeded as interrupts and vectors also holds the branch logic, which none of this reaches and the card counts. Click a bead and the card reads the pin's level (the level, not a meaning: they are active low), names the nodes, and says what moved. The dash-dot beads are the branch logic, and the wiring splits it into three on its own. From every node the die gave a branch word the rule walks back through gate inputs and switch channels inside the interrupts block and the static logic, stopping where a node reads anything from outside: the instruction register, the flags, the data bus, the adder. What those cones reach falls into three connected pieces. One is #BRtaken, an AOI that is the opcode's polarity bit (ir5) against the flag its top two bits select, the flag multiplexer written in switches: is the branch taken. One is branch-back and its latches, reading the offset's sign at T2 of a branch: which way. And short-circuit-branch-add stands apart, joined to the direction only through the controls of its own switches, reading the adder's carry or its complement when the branch is backward: does it cross a page, and if not the instruction ends early, on the wire this piece feeds into the timing chain's reset. The card for each lists the nodes, what the piece reads at its edge and what it feeds, all measured, with the levels now. The orange outline is the decimal correction, the circuit the designer page counts by five names, here taken as everything those names and their kin are wired into: from every node the die gave a decimal name (the two control lines #DAA and #DSA, the two nibble detectors DC34 and DC78, and the DA- family in the adder) the rule walks both ways inside the static logic, stopping where a node reads or writes anything outside. It comes out as one piece, and what it reads and feeds is the whole mechanism read off the wires: it reads the adder's products and the D flag's pipeline copy, and it feeds the two carries the detectors inject and the adjusted special bus, bits one to three and five to seven, which is where six is added to a nibble over nine on the way to the accumulator. The card sorts the nodes by which walk found them, detect, enable and adjust, with the levels now. The square-dotted beads are the registers as the die builds them, S, A, X and Y, and the lines that move each. A register is everything reachable from its eight bits through unnamed nodes and nodes named after it, which stops at the buses: S is four nodes a bit (the bit, its inverse, two latch nodes) and its switches reach exactly the special bus and the address-low bus, the two buses S can meet; X and Y are three a bit and meet the special bus alone; A is three a bit and meets the special bus, the decimal-adjusted bits and the data bus. The lines are the controls of those switches, less the clocks, and each comes with the cone that makes it, walked back inside the control pipeline and the static logic to where it reads a decode term, which is the instruction set written in the wires: SS holds S (asserted by the absence of any term), SBS loads it and is made from TXS, SSB drives it onto the special bus from TSX, SADL puts it on the address-low bus from JSR and the stack terms; SBX and SBY load X and Y from LDX and LDY and the increments, XSB and YSB drive them out for the indexed modes; SBAC loads A from LDA, PLA, TXA, TYA and the ALU's results, ACDB drives it onto the data bus for STA, CMP and PHA, ACSB onto the special bus for TAX, TAY and the shifts. Lines that share a node share it as a bead of its own. A register's card reads its byte off the chip; a line's card says whether its eight switches are open at this half-cycle and what it is made from. The red outline is the program counter's incrementer, what lies between the counter and its next value: from the sixteen outputs that become the prime latches, and from the increment enable and the two carries the die names, the rule walks back inside the static logic and the Program counter block, never entering the counter's own storage, and finds one piece that reads exactly the sixteen counter bits (plus what enables the count: the branch logic's page short circuit among them) and feeds exactly the sixteen prime latches, the carry rippling nine deep through bit seven. The card sorts it into enable, low byte and high byte, and reads PC off the chip. The ringed beads are the status register and its flag logic. Each flag bit is a dynamic node loaded from one AOI whose legs are a source and its enable, the data bus and the PLP/RTI load, a set or clear and its enable, and the bit's own pipeline copy for the hold; the rule walks back from each bit inside the status block, the static logic and the control pipeline, always through that AOI (it is exactly where the outside arrives: the carry, the bus, the instruction register) and then stopping wherever a node reads from outside. What one flag alone reaches is its logic; what two reach is shared, and that is the polarity of the set/clear pairs read off ir5 and the PLP/RTI load. C reads the ALU's carry, Z a NOR over all eight data-bus bits, N the bus's bit seven, V the ALU's overflow and the S.O. pin, I the BRK sequence; and B is not a stored bit at all but an inverter of the timing chain's D1x1, read fresh each time P is pushed, which is why a pushed P can tell a BRK from an interrupt when the register cannot. The Pout bits, each the inverse of a flag's pipeline copy opened onto the data bus for PHP, are a bead of their own. A flag's card reads its bit off P and names what it reads. The blue beads are the address latches, the two latches that hold the address on the pins. The register recipe misreads them, and the way it misreads is the structure: the latch nodes are themselves switch controls, gating the pull-ups of their own pad drivers. Read on its own terms each bit is a chain of seven nodes, the bus bit's inverter, a node under cp1, the latch input under the load line, its inverse, an output latch under cclk, and the two static nodes of the pad's push-pull driver; the closure of the eight bits over unnamed and own-named nodes reads exactly the address bus and feeds exactly the pads. The load lines, ADL/ABL and ADH/ABH, come with the cones that make them, and the low one reaches the store-data pipeline, which is the latch not reloading during a store's data cycles. Two more beads are the constant generators the die names: the three low address bits forced for the vectors, inverters of the vector bits, and the high byte forced to zero for the zero page and one for the stack, made from exactly those addressing-mode terms. A latch's card reads the byte it holds off the pins; a line's says whether its eight switches are open and what it is made from. The beads in a hue per bit, warm low to cool high, are the ALU and its adder, and they are derivable because the die names the adder bit by bit: the AND and OR terms, the XOR, the sum, the carries alternating in polarity, the result select, the hold register. From each hold bit the rule walks back inside the ALU and the static logic, stopping at the inputs, the decimal nodes (which have their own bead) and the carry ends, and a node belongs to the bit that reaches it soonest: ten or eleven nodes a slice, the carry into a bit filing with that bit because that is what its sum reads, and the seven generate terms shared between neighbours because two bits reach each at the same depth. The inputs are two more beads, A its eight bits and B sixteen, an inverter a bit for the inverted data bus that makes SBC; the carry in, carry out and overflow three more, by name with what makes them; and the thirteen control lines sit in three beads by what they do, the five ways in, the five functions, the three ways out, each with its cone. A slice's card reads its bit and the whole ALU byte off the chip; an input's its byte; a line group's which lines are high now. The teal and orange beads are how the chip meets memory: the input data latch, four nodes a bit from the pad's inverter through notidl and idl to a latched copy that three lines open onto the internal data bus and the two address buses; the data output register, six a bit, loaded from the internal bus and driving the pads through a push-pull driver under the write control; the internal data bus as its eight bits alone, because its closure over unnamed nodes reaches most of the chip, with every line that holds a switch on a bus bit listed on its card and the ones that are nobody else's given their cones here; and the read/write control, the cones of the four nodes the die names for it, which read the write latch, ready and reset: a write needs the chip ready and not in reset, and that is read off the wires. A latch's card reads its byte off the chip; the bus's its byte and its lines; the control's the pin. The gold beads are the instruction register and its predecode. An opcode arrives on the pads, is latched as the predecode byte, three nodes a bit, with clearIR forcing it to zero, which is BRK, for an interrupt; it passes under fetch along a load path of three more nodes a bit into the register, ir and notir, which feeds over a hundred decode terms directly and sixty-three more through irline3, a derived line for the two low bits both zero. Two closures over the block's unnamed nodes find those three: what only the predecode reaches, what only the register reaches, and the path both reach. The predecoder is a bead of its own, the five terms and ONEBYTE that read the predecode byte for what the timing chain wants early, a two-cycle instruction or a one-byte one, feeding the T0 cell and the counter's increment enable. The cards read the predecode and the register off the chip, say whether fetch is open, and which predecode terms are high. The special bus is eight pure bus bits: no gate drives them, the clock precharges them to vcc, and everything else reaches them through a switch. Thirteen lines hold a switch on every bit, and each line's direction is read off the far side of its switches rather than off its name: a far node driven by a static gate is a source, so the line brings a value onto the bus; a far node that is a latch or a precharged bus is a sink, so the line takes the value off; a far node that is itself a bus joins the two. Six lines come out onto, six off, one the link to the data bus. The decimal-adjusted copy is a bead of its own, the six gates that combine a bit with the adjust and the inverters they read, with no bits zero and four because adding six never changes them, and the accumulator is loaded from those. The one line nobody else cones, the bus onto the high address byte, is drawn with its cone, which reads the branch decoder. The bus card reads the byte on the bus and every line's direction and level. The amber beads are the store-data pipeline, the machinery whose latches kept turning up at the edge of everything else: the address latches' load line reads them, the write control reads them, the carry-in choice reads them. The die does not name it; the simulator's own timing readout does, as the bracket in its trace. A detect gate NORs the five data-cycle terms, one per addressing mode, with the read-modify-write classes; it latches under the clock into SD1, which holds itself when the chip is not ready, and SD1 delayed one cycle is SD2. What they feed is why every store works: the write control, the address latch's hold (the address stands still through the data cycles), the shift gating of a read-modify-write, and the carry flag's shift path. The cards read each latch's level off the chip and name what it feeds. The sky beads are the ready logic, the wire nearly every container before it read at its boundary. The RDY pin's receiver runs through one NOR that also reads the write control, and that single gate is the famous rule: a low RDY never stalls a write cycle. It latches into notRdy0, the master, one dynamic node, active low as its name says, read by thirty-odd nodes: the timing chain's hold, the flags' loads, the program counter's increment enable, the write control, the store pipeline. Five copies joined to it under the other clock phase and a two-latch delay chain re-time it, which is how a consumer asks whether the chip was ready last cycle. The receiver's card reads the pin, the master's says stalled or ready off the chip, the copies' names what they feed. Three last pieces round out the set. The program counter's own storage is four bytes of eight pure bits each, the counter pair and the next-value pair, with six lines: hold, load from the buses (a jump landing), and drive onto them (the next fetch); the high pair's lines read the hidden T1 and the branch logic, which is a taken branch reloading the high byte a cycle after the low. The pipeline latch file is every node the die names pipe-something, fifty-two latches and every one under the same clock, the file where the decoder's phase-one answers are re-timed onto phase two; fifteen carry names, thirty-seven are pipeUNK, named by the reverse engineers for what they could not yet place. And the SYNC generator is four nodes: the pin that says this cycle is an opcode fetch is the hidden T1, inverted twice and sent off chip, the whole generator reading exactly one wire. Any of these can be folded into one node: collapse on its card, or c with it selected, and collapse the blocks folds all twelve at once. The one liberty taken with position is stated: the node sits at the mean of its members' centroids, which is still a measurement. Its members and the edges among them go; every edge that crossed its boundary is gathered into one line per far end, as wide as the number it stands for. Per half-cycle the node is lit by the share of its members that are high and ringed if any changed, and a bundle flashes if any edge in it fired or toggled. A node in more than one folded container goes to the most specific, so a capsule folded inside a folded block keeps its own node and the block's node stands for the rest. Click a folded node to select what it stands for; expand on the card, or expand all, unfolds. A convex hull per block was measured first and rejected, because the datapath blocks are interleaved bit-slices: the address latches' hull contained every node of the ALU and the program counter, which is the opposite of a container. The unclassified residue and the static logic get no region, being the background the twelve blocks sit in.

A node with a dashed outline has no pullup: a transistor pulls it to vcc, and its pulldowns either discharge it or leave it holding charge. For most of them that transistor is a clock, and the node is precharged, which is how the decode lines and sync work and why the chip has a minimum clock speed. For the address and data pads the same shape is the pull-up half of a push-pull output driver. A solid outline is a static gate output, held high by a depletion pullup, or a wire that takes whatever it is joined to. Which is which is read from the same file the workbench draws its gates from, and clicking a dashed node names the transistor's gate.

The list under the code says the same thing in words: every node that changed level, grouped by block, with the way it went. Click a name and the drawing flies to it. Turn on show only what moved and the rest of the chip steps aside.

Fullscreen is the workbench's study view: the drawing takes the whole screen and everything else rides on one floating console, a strip of icons with a drawer beside it. The drawers are the registers, the watch, the code, the moved list and the view controls, one at a time; the transport is on the strip; the strip is the handle, so the console goes wherever it is least in the way, and it remembers where that was.

The watch list takes stems as the die names them (abl, adh, idb) and shows each as the bits it is, high bit first, with the ones that moved at this half-cycle marked, and as a thin line through those bits on the drawing so the latch reads as one thing. Click a row to fly to it. The default set is the two address latches, the two internal address buses, and the three data buses, which is enough to watch an address form and a byte arrive.

The code beside it is the program's own source, with the instruction being fetched marked and a count of how many times each has been. At the slowest clocks every fetch is seen; at the fastest the chip runs many half-cycles between frames and the head line says how many, because a drawing that claims to show one half-cycle while showing forty would be the wrong kind of convincing.

Positions are the same centroids the die graph draws, read out of the geometry the explorer uses. Edges and blocks come from schematic.json, the file the workbench walks. Levels come from the running chip, the same one every page here runs. The trace follows one opcode through the same half-cycles with the wires that are one wire; the halfshot records them. This page is for watching all of it happen at once.