Measured · not looked up
Follow one
instruction.
Pick any of the 256 opcodes. It is assembled into memory, the chip fetches it, and everything below is read back out of the silicon afterwards: the registers as they mutate, every node that changed level, and the wires that are shorted together while it happens.
Nothing here consults a table of what an instruction is supposed to do. The cycle counts are free to be wrong, which is what makes them worth something when they are right.
Loading the chip…
The chip never fetched that instruction: it jammed before reaching it. Twelve opcodes do this and the Timing page names them.
One wire, right now
A node's level is a property of the group it is joined to, not of the node. When a pass transistor is open the two wires either side of it are not two wires holding the same value. They are one wire. Freshly joined groups are marked.
What moved
Switches on this bit
| cyc | φ | T-states | AB | DB | R/W | A | X | Y | S | P | PC | Δ |
|---|
Every row is one half-cycle. Click one to jump to it. Δ counts the nodes that changed level since the row above.
Why it runs past the end
The result is not in the register when the instruction ends
The 6502 overlaps the tail of one instruction with the next opcode fetch. An ALU result is not in the accumulator when sync rises. It is sitting in the adder's hold register, and it transfers during the cycle that belongs to the next instruction.
So this trace deliberately runs past the next sync and marks those rows as the tail. Stopping at the boundary would show the instruction not having happened, which is the most misleading thing this page could do, and it is what a behavioural emulator hides, because it writes the register at the end of the instruction where you expect it. Trace ADC and watch the accumulator change a cycle after the instruction is over.
The way in
A pin is not a wire
Following the data pins into the chip finds nothing. All eleven of db0's connections go to a power rail, because a pin is an output driver: nothing enters the chip from a pin through a pass transistor at all. The way in is the input receiver, which is a gate, and the first wire that behaves like a wire is idl, the input data latch.
That is why the group above starts at idl and idb rather than at the pins, and it is a fact about the die rather than a convenience: a trace that follows only switches can never leave the pad ring.
Scale
Most of what conducts is not a wire either
At any instant 1503 of the 3510 transistors are conducting, and about 165 nodes change level every half-cycle, a tenth of the chip, at every edge. Lighting up everything that is on would produce a picture of the whole chip and tell you nothing.
But the datapath is not that graph. Almost all of what conducts is pulldowns inside gates rather than switches joining named wires, so walking only open pass transistors from the internal data bus reaches a median of three nodes. The accumulator is joined to the data bus in two half-cycles out of ninety, and when it is, the path is two switches long: SBDB then SBAC. That is what the panel above is showing.
What is not shown
One bit at a time, and the eight differ
The wire panel watches a single bit, because the eight are genuinely different circuits and merging them would make a join look wider than it is. Bit 7 of the special bus is opened by ADDSB7 where bits 0–6 share ADDSB06, and that difference is the shifter. Move the bit slider and watch which joins appear and disappear.