Derived · not drawn
The datapath,
derived from the switches.
The die view shows the 6502 as it is: a photograph's worth of polygons, accurate and hard to read. This is the same chip with the geometry taken away, leaving buses as lines, registers as boxes, and a switch wherever the silicon has one.
Nobody drew it. Every unit, every path and every control line below was found by looking at which transistors join which nodes, and the layout keeps the die's own order: columns run left to right as they do on the chip, rails stack in the order they sit inside a bit row.
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How to read it
A lit switch is a wire
Each small square is a group of eight pass transistors, one per bit. When the control line named beside it goes high, those eight transistors conduct and the two things they sit between stop being separate wires: for that half-cycle they are one net at one value. That is the whole mechanism by which a byte moves inside a 6502. There is no bus arbiter and no datapath multiplexer, only switches that the decode PLA opens.
Watch SBAC and ADDSB06 during an ADC: the adder's result reaches the special bus a full cycle before it reaches the accumulator.
What it leaves out
159 of 3510 transistors
This diagram accounts for the bus fabric and nothing else. The 6502 is roughly three-quarters pass transistors, and only a slice of those are the byte-wide paths drawn here; the static gates, the decode PLA that drives every control line named above, the timing chain and the pad ring are all outside it. The count in the header is the honest fraction, kept in view on purpose.
An idealised picture that hides how much it idealised is worth less than one that states it. For the part this drawing cannot show, the die view carries all 3510.
Where the shapes come from
Order preserved from the silicon
Columns are ordered by each unit's mean position across the die, so left and right mean what they mean on the chip. Rails are ordered by where the wire sits inside a bit row. A bus crosses all eight rows, so its average height says nothing, but its offset against its own row is consistent, and that offset is the order drawn. Both are order-preserving remaps: move something on the die and it moves here.
The one place the drawing departs from measurement is the bit rows themselves, which come from the bit index in each node's name rather than from its position. On ADH those two disagree: it carries the constant generators for stack access and vector fetches, and that extra geometry drags bits 2 and 3 out of order. The names are right and the centroids are misleading, so the names win.