Transistor-level · from the real die

The MOS 6502,
simulated switch by switch.

Nothing here models the 6502's behaviour. The simulation holds 1725 nodes and 3510 transistors taken from the die, and the behaviour is what those switches do. Register values are read back out of storage nodes; cycle counts are counted, not looked up.

Run the chip What is on screen

…

die · live Program

drag to pan · pinch or scroll to zoom · tap a wire to trace it

Registers

PC0000

A00

X00

Y00

S00

executing none

Bus & timing

Address0000

Data00

Directionread

Cycle0

Half-cycle0

Clockφ1

SYNC CLK0 R/W

Selection

Nothing selected. Tap a wire on the die.

Highlight the whole connected group

Lab: one instruction, end to end

Instruction

Layers

Inactive brightness Glow Invert scroll zoom

Reading the die

Glowing

The node is logically high at this instant. Not an animation: 3,510 switches solved to a fixed point, twice per clock cycle, then painted.

White

Everything electrically connected to your selection right now. It changes as transistors open and close, because a wire is not a fixed thing.

Dim

Inactive, or one of the two power rails. vss and vcc blanket the die, so they are deliberately muted rather than drawn live, or every trace would light the whole chip.

Mask layers

Transistors

There is no transistor layer to switch on. A transistor is the crossing: polysilicon passing over diffusion, 3,510 times. That is the whole of the logic: no gates, no decoder, nothing above the switches.

Pins

SYNC rises on an opcode fetch. CLK0 is the input clock; the chip does work on both of its edges, which is why time is counted here in half-cycles. R/W is the bus direction, high for a read.

Memory

follow bus

Clock

The die view

What is on screen

The die is real

Every polygon comes from the visual6502 team's trace of a decapped 6502: 8,233 shapes across six mask layers, triangulated into 83,227 triangles. Metal is drawn translucent on top, in the order the mask layers sit on silicon.

Brightness is node level

A node is drawn lit when it is high. Nothing is animated: 3,510 switches are solved to a fixed point twice per clock cycle, and the resulting levels are uploaded to the GPU as a 1725-byte texture.

A wire is not a fixed set of nodes

Tap any trace to see what it is connected to at that instant. The connected group is recomputed as transistors open and close, because a level belongs to the group a node is joined to rather than to the node.

The Lab

One instruction, half-cycle by half-cycle

The 6502 has no instruction decoder in the sense a textbook means. An opcode is a byte that lands in a latch; a PLA turns those eight bits into about forty control lines; those lines open and close switches that connect registers to buses. There is no microcode and nothing to step through: the decode is combinational, a pure function of what is in the instruction register at that moment.

The Lab follows a single instruction through that, a half-cycle at a time, framing the die on whichever part is doing the work. The control lines it lists are read out of the running chip at that instant rather than written down here, so the narration can be checked against the silicon.

LDA: a byte into a register ADC: the accumulator lag INX: adding one, the hard way STA: out through the pins

The ADC link opens at +5 half-cycles, where the adder holds the sum and the accumulator still holds the old value.

The Blueprint

The datapath with the geometry removed

The die view shows 3510 switches where they actually sit, which is accurate and hard to read. The Blueprint draws the datapath as a block diagram instead: buses as lines, registers as boxes, a switch wherever the silicon has one, running off the same engine.

Nobody drew it. Every unit and every path was found by asking which transistors join which nodes, and each one is labelled with the decode line that opens it. It accounts for 159 of the 3510 transistors, and it says so on the page.

Open the Blueprint Watch Fibonacci move

Try this

The accumulator lags the ALU

The 6502 does not put an ALU result into the accumulator when the instruction ends. Run ADC and step one half-cycle at a time: it reaches the next opcode fetch with A still holding the old value. The result is sitting in the ALU's hold register, and it transfers a cycle later. LDA, which bypasses the ALU, lands a cycle earlier.

An emulator that commits results at instruction boundaries cannot show this, because the boundary it commits at does not exist on the die.

Verification

Two oracles, either alone insufficient

Against the original

A headless harness runs the original visual6502 JavaScript and dumps the level of all 1725 nodes at every half-cycle. This engine matches bit-exactly. Matching registers would only show agreement about the 6502; matching every node shows agreement about the silicon.

Against the datasheet

Documented cycle counts including page-crossing and branch penalties, the read-modify-write double write, JSR/RTS stack layout, ADC/SBC flags, decimal mode. A shared misreading of the die data would pass the first test and fail this one.

Throughput

About 28,500 half-cycles per second natively, roughly 94× the original JavaScript. The renderer redraws in six draw calls at any zoom, because the layout never changes and only a 1725-byte level array is uploaded per frame.

Credit

Where the die data came from

This exists because the visual6502 team decapped a 6502, photographed the die, traced it by hand, and gave it away. Greg James, Brian Silverman, Barry Silverman, Ed Spittles, Segher Boessenkool, Achim Breidenbach, and everyone else who contributed.

That site is failing. Its wiki, a decade of research on the 6502, returns HTTP 500 on all 169 pages, and the 2.3 GB of die photography is still served correctly but nothing links to it any more. All of it is mirrored here, with the wiki rebuilt from Internet Archive captures: the archive.

The visual6502 archive Source visual6502.org

Code is MIT. The die geometry is CC BY-NC-SA 3.0, attributed to Greg James and www.visual6502.org, and those terms carry to this deployment.

Visual 6502

The MOS 6502,simulated switch by switch.